Redundancy circuit and method for semiconductor memory

Details Redundancy circuit and method for semiconductor memory Redundancy circuit and method for semiconductor memory

1999-05-20

2000-12-05

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365 51, 365 63, 365205, 36523003, G11C 700

Patent

active

061575844

ABSTRACT:
A redundancy configurations is described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which plural redundant rows (or columns) are provided to replace more than one defective row (or column) in an array or subarray. Redundancy configurations are further described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which a given redundant row (or column) may replace a defective row (or column) in one of plural subarrays representing distinct sets of rows (or columns).

REFERENCES:
patent: 5495445 (1996-02-01), Proebsting
patent: 5497347 (1996-03-01), Feng
patent: 5572471 (1996-11-01), Proebsting
SMD-K6.RTM.-III Processor Data Sheet, 21918A/0-Feb. 1999, Chapter 2, pp. 5-20.

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