Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-04-27
1994-09-20
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365 96, 36523003, G11C 1140
Patent
active
053495551
ABSTRACT:
In order to obtain a redundancy circuit which can freely arrange its fuse in a required position with disciplined accessibility after employment, a combination circuit (50) receives outputs (QA0 to QA7) obtained by decoding a column address (AXM) by a column line decoder (2), signals (QB0 to QB7) indicating a faulty line, signals (L0 to L7) generated from the signals (QB0 to QB7) and an inverted signal (ENB*), to generate signals (YS0 to YS8) for controlling selecting switches for specifying column lines. If a K-th column line is faulty, a column line selecting switch for selecting the K-th column line is forcibly turned off and an (N+1)-th column line is allocated with respect to specification of an N-th column line (N.gtoreq.K). Thus, fuse positions of redundancy circuits can be standarlized between products so that the products can be easily mass-produced and supplied at a low cost even if the redundancy circuits are contained in small quantities of various ASICs.
REFERENCES:
patent: 4908798 (1990-03-01), Urai
Fears Terrell W.
Mitsubishi Denki & Kabushiki Kaisha
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