Redundancy arrangement for novel memory architecture

Details Redundancy arrangement for novel memory architecture Redundancy arrangement for novel memory architecture

1998-10-23

2000-06-20

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523006, G11C 700

Patent

active

060785357

ABSTRACT:
A semiconductor memory device having a redundancy scheme is disclosed. A memory cell array includes a number of standard word lines sets and at least one redundant word line set. Each standard word line within a standard word line set is selected by lower address signals, and couples memory cells to a different combination of bit line than the other standard word lines within the standard word line set. In a standard mode of operation, transfer gates coupled to each bit line are enabled according to the lower address signals. Each redundant word line within a redundant word line set is selected by a defective address, and couples memory cells to a different combination of bit lines than the other redundant word lines within the redundant word line set. In a redundant mode of operation, the transfer gates are enabled according to an activated redundant word line to ensure that the proper combination of bit lines is coupled to sense amplifier circuits. In this manner, any of the redundant word lines within a redundant word line set may be utilized to replace any of the standard word lines, even if the replaced standard word line couples memory cells to a different combination of the bit lines than the replacing redundant word line.

REFERENCES:
patent: 4918662 (1990-04-01), Kondo
patent: 5347484 (1994-09-01), Kwong et al.
patent: 5579269 (1996-11-01), Yamamoto

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