Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-11-22
2005-11-22
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S225700, C365S185090
Reexamination Certificate
active
06967878
ABSTRACT:
A redundancy architecture for improving the throughput of testing and repairing the semiconductor memory after packaging. A memory device is composed of a memory cell array including memory cells and first redundant cells, a data comparator comparing read data received from the memory cell array with anticipated data provided by an external tester to produce a data mismatch signal, a redundancy mapping circuit responsive to the data mismatch signal for detecting a defective address of the memory cell array, a nonvolatile memory storing the detected defective address, and a redundancy circuitry repairing the memory cell array by replacing ones of the memory cells associated with the defective address with the first redundant cells.
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Elpida Memory Inc.
Phan Trong
Young & Thompson
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