Redundancy architecture for an integrated circuit memory

Details Redundancy architecture for an integrated circuit memory Redundancy architecture for an integrated circuit memory

2011-04-12

2011-04-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S195000, C365S225700

Reexamination Certificate

active

07924638

ABSTRACT:
An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

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patent: 6320801 (2001-11-01), Kwak
patent: 7420859 (2008-09-01), Nautiyal
patent: 7495976 (2009-02-01), Mittal et al.
patent: 2008/0266990 (2008-10-01), Loeffler
patent: 2009/0168569 (2009-07-01), Ryu

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