Redundancy architecture and method for block write access cycles

Details Redundancy architecture and method for block write access cycles Redundancy architecture and method for block write access cycles

1995-06-05

1999-05-04

Lane, Jack A.

Static information storage and retrieval

Read/write circuit

Bad bit

365195, 365200, G11C 700

Patent

active

059010932

ABSTRACT:
An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements.

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