Reduction of the shear stress in copper via's in organic...

Details Reduction of the shear stress in copper via's in organic... Reduction of the shear stress in copper via's in organic...

2006-06-13

2006-06-13

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S626000, C438S627000, C438S637000

Reexamination Certificate

active

07060619

ABSTRACT:
Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

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