Reduction of switching noise in integrated circuits

Details Reduction of switching noise in integrated circuits Reduction of switching noise in integrated circuits

1999-12-30

2001-12-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S021000, C326S027000

Reexamination Certificate

active

06329834

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the reduction of switching noise in CMOS gates and drivers.
Typical CMOS gates and drivers consist of a complementary pair of MOS gates, one n-type
10
and one p-type
11
, as illustrated in FIG.
1
. Gate
11
is connected to input
18
, output
17
, and low voltage source VSS. Gate
10
is connected to input
18
, output
17
, and high voltage source VDD. When input
18
is low, transistor
11
is conductive and transistor
10
is nonconductive. Output
17
is connected to VSS and therefore has a low value. When input
18
is high, transistor
11
is nonconductive and transistor
10
is conductive. Output
17
is connected to VDD and therefore has a high value.
With the input
18
in the high or low state, the output
17
is fairly stable. However, as the input
18
transitions from either high-to-low or low-to-high, there is a period in which both gates are partially on at the same time. Connection of VDD and VSS cause a drop in the potential difference between these reference potentials. The output driver load also possesses capacitive reactance which must be charged or discharged during transition, causing a current spike on VDD and VSS during charging or discharging of the output load capacitance. These voltage disruptions can cause circuit noise.
There is a finite and nonnegligible inductance L that exists between each gate
10
and
11
and the external power supply. The current spike through this parasitic inductance L results in a small dip in VDD and a small bounce in VSS at the gate. This effect is known as ground bounce. Ground bounce can cause noise which can propagate throughput a chip, resulting in an operator error. Some degree of noise can be reduced through the addition of decoupling capacitors across the power pins of integrated circuits. However, parasitic inductance continues to exist between the internal gates and the external decoupling capacitors. The effects of parasitic inductance responsible for switching noise cannot be completely removed by external decoupling capacitors.
The severity of ground bounce increases with the number of gates switching simultaneously. As bus widths get wider, this problem becomes more serious. The greater the number of simultaneously switched inputs, from high-to-low or low-to-high, the greater the severity of ground bounce.
Ground bounce results from the parasitic inductance of the IC and packaging interconnects. It can be especially troublesome in ICs that employ high speed transistors. During switching, when a transistor switches states, current is passed through these parasitic inductances at a changing rate. Change in current through an inductor produces a voltage across the inductor. The resultant current spike results in a bounce in the voltage source/drain of the transistor. This in turn changes the gate-to-source voltage of the transistor. This change in gate to source voltage is known as “ground bounce” in which the source or drain voltage falls above/below the nominal voltage for a period of time before recovering.
Source bounce and ground bounce both result from voltage spikes on the power network caused by logic transitions. There are adverse consequences of such voltage spikes. They reduce operating voltage which can delay or prevent circuit operation. Also, erroneous operation may occur because these voltage spikes may be transmitted through to the gate outputs. Noise can propagate throughout the part, resulting in an operating error. A typical high-speed CMOS chip will contain many such drivers that all share common on-chip power rails, e.g., nodes VDD and VSS. As bus width increases, this problem becomes more serious with the worst case scenario having all the bus drivers transitioning simultaneously from either high to low or low to high when a large spike is transmitted through to the outputs.
Ground bounce in actively switching circuits is recognized in the prior art. Methods are known for controlling ground bounce for channels that are actively switching their outputs, such as U.S. Pat. No. 4,933,574 to Lien et al., and for addressing the problem of quiescent channels that are already low and become unsettled by local ground bounce induced by a neighboring output channels, such as U.S. Pat. No. 5,319,260 to Wanlass. U.S. Pat. No. 5,124,579 to Nagshineh modifies the output drive with RC delay circuits to minimize ground bounce during active switching by including resistive means connected in series with certain gates of the pull-up and pull-down transistors, thereby limiting the rate of increase in voltages. Use of voltage feedback means to regulate voltage change rates is taught by U.S. Pat. No. 5,148,056 to Glass. These approaches require additional and complex circuitry and introduce switching delays. As bus widths increase, the number of additional components required by these approaches and the delays introduced may become unacceptable.
SUMMARY OF THE INVENTION
The present invention provides a dynamic current assist to the VDD and VSS power rails of an integrated circuit to reduce ground bounce by adding charge to VDD and drawing charge from VSS during the transition period of a gate. Two pairs of CMOS gates are added to dynamically connect the CMOS gate dynamically to a voltage potential above VDD and to a voltage potential below VSS as needed to assist in transitions from low-to-high and/or high-to-low. According to the present invention charge is dynamically added to the VDD node as it is needed and dynamically drawn from the VSS node as it is needed.
More specifically, the present invention provides a circuit for reducing bounce or switching noise in integrated circuits by adding two more pairs of CMOS gates in parallel with those in the original circuit such that the input of all three gates is tied to the same input signal. The VDD node of the original CMOS gate is connected to a voltage rail slightly above VDD (VDD+V), and the VSS node of the original gate is connected to a voltage rail slightly below VSS (VSS−V) through the two additional gates. In a circuit according to one embodiment of the present invention an instantaneous power assist is provided to a CMOS gate or driver by colocating on the device these two additional pairs of CMOS gates.
According to another embodiment of the present invention an enhancement of this instantaneous power assist is achieved by adding a resistance to the gate of one gate of the additional CMOS gate connected to the VDD node of the original CMOS gate and to one gate of the other additional CMOS gate connected to the VSS node of the original CMOS gate. The addition of these resistances will slightly delay the on/off times of these gates such that the one connected to the original VDD rail will pulse on sooner, causing an increased VDD when the gate input changes from low to high, and will pulse on slower when the input changes from high to low. Similarly, the other resistance will cause its associated gate connected to the original VSS rail to pulse on sooner when the input changes from high to low and to pulse on slower when the input changes from low to high. The net effect is that when the output is transitioning from low to high, it will get an extra boost (VDD+V) from the CMOS gates added to the original VDD rail, while the added drain from VSS−V will be blocked by the CMOS gates connected to the original VSS rail. The converse is also true as the output transitions from high to low.
In yet another version of the current invention, the VDD+V and VSS−V power references may be generated by on-chip charge circuits, making the circuit self-contained.
Even though the VDD+V and VSS−V power rails suffer from the same parasitic inductance between the CMOS gate and the power supply, the fact that VDD+V is greater than VDD and that the gates are colocated on the device means that the power assist will be instantaneous and will be limited only by the inductance if the amount of the current drawn causes VDD+V to dip down to VDD (or VSS−V to

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