Reduction of silicon defect induced failures as a result of impl

Details Reduction of silicon defect induced failures as a result of impl Reduction of silicon defect induced failures as a result of impl

1998-09-30

2000-05-30

Niebling, John F.

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

438419, 438526, H01L 12331

Patent

active

060690488

ABSTRACT:
A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of the integrated circuit. The buried layer implant is the final implanting step during fabrication of the integrated circuit structure. In another technique, fabricating the integrated circuit structure includes performing multiple sequential processes some of which are performed at elevated temperatures above about 500.degree. C. A buried layer is implanted beneath a surface of the integrated circuit. After implanting the buried layer, the substrate is subjected to a fabrication process at an elevated temperature above about 800.degree. C. only once. Propagation of defects, such as in-the-range defects or ion enhanced stacking faults, from the buried layer to other device layers during the fabrication process is reduced.

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