Reduction of shrinkage of poly(arylene ether) for low-K IMD

Details Reduction of shrinkage of poly(arylene ether) for low-K IMD Reduction of shrinkage of poly(arylene ether) for low-K IMD

1999-06-21

2002-12-17

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S624000, C438S637000

Reexamination Certificate

active

06495478

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of dielectric layers employed within microelectronics fabrications. More particularly, this invention relates to the formation of dielectric layers disposed among inter-level metallization and conductive layers within microelectronics fabrications.
2. Description of the Related Art
The manufacture of microelectronics fabrications makes use of conductor and semiconductor layers formed and patterned upon substrates to form electrical circuits. It is necessary to separate these electrically conducting layers from each other by insulating layers of dielectric material. In addition to being non-conductors of electricity, these dielectric layers must be capable of being formed to exacting physical specifications and must be able to withstand subsequent microelectronics fabrication operations and device operating conditions. Of particular importance is the ability to function satisfactorily over a wide range of temperature.
Advances in speed and performance requirements, along with decreases in dimensions and ground rules for microelectronics devices, have made the requirements placed upon such dielectric layers more stringent with respect to lowering the “relative dielectric constant” of the dielectric layers i.e. the dielectric constant relative to vacuum, hereinafter referred to for brevity as the dielectric constant). Lower dielectric constant dielectric layers are desirable disposed between and around the patterned microelectronics conductor layers within microelectronics fabrications since such lower dielectric constant dielectric layers typically provide microelectronics fabrications with reduced parasitic capacitance and attenuated patterned conductor layer cross-talk
Within the art of microelectronics fabrication, it is conventional to employ dielectric layers formed from silicon containing dielectric materials. Silicon containing dielectric materials including but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric layers formed between and around patterned microelectronics conductor layers within microelectronics fabrications are generally satisfactory. However, such dielectric materials typically exhibit dielectric constant values which range from about 4.0 to about 9.0 when formed into dielectric layers formed between and around patterned conductor layers, and it is therefore desirable to employ alternate methods and materials for forming dielectric layers having lower dielectric constants.
Of the methods and materials which may be employed for forming lower dielectric constant dielectric constant dielectric layers disposed between and around the patterns of patterned microelectronics conductor layers within microelectronics fabrications, methods which employ dielectric materials with intrinsically low dielectric constants are particularly desirable within the art of microelectronics fabrication. Such alternative low dielectric constant dielectric layers may be formed on microelectronics substrates by spin coating of intrinsically low dielectric constant materials including but not limited to organic polymer spin-on-polymer (SOP) dielectric materials. Such dielectric layers typically exhibit somewhat lower dielectric constants than those of silicon containing dielectric materials, ranging from about 2.5 to about 3.0. In particular, organic polymer spin-on-polymer (SOP) dielectric materials which may be employed for forming dielectric layers include but are not limited to polyimide organic polymer dielectric materials, poly (arylene ether) organic polymer dielectric materials and fluorinated poly (arylene ether) organic polymer dielectric materials. Such organic polymer spin-on-polymer (SOP) dielectric materials are typically thermally cured after spin coating in order Lo form stable dielectric layers from the spin-on-polymer (SOP) dielectric materials. The thermal curing process is generally regarded as necessary to accomplish the removal of solvents, plasticizers and related substances from the organic polymer dielectric layer, as well as to insure the proper degree of polymerization within the organic polymer dielectric layer.
The magnitude of the dielectric constant as well as the stability of the physical and chemical properties of the spin-on-polymer dielectric layer are largely determined by the degree of polymerization of the organic polymer and the amount of residual material remaining within the organic polymer dielectric layer. Hence conventional curing methods after forming organic polymer spin-on-polymer (SOP) dielectric layers employed in the art of microelectronics fabrication by spin coating generally employ thermal annealing at elevated temperatures and may also employ specified environmental conditions during the curing process.
Particularly suited to use between multiple interconnection conductor patterns as inter-level metallization dielectric (IMD) layers are organic polymer dielectric materials. Such organic polymer materials as, for example, the poly (arylene ether) thermoplastic polymers possess outstanding dielectric properties such as low dielectric constant and high breakdown voltage, and are readily formed into dielectric layers employing spin-on-polymer (SOP) coating methods. With appropriate curing, such organic polymers may be employed in conventional microelectronics fabrications wherein resistance to thermal and environmental stresses is a significant requirement.
The application of organic polymer dielectric layers as dielectric layers disposed around and between conductor layers as inter-level metallization dielectric (IMD) layers is not without its problems. The organic polymer dielectric layer must be properly cured to avoid physical or dielectric degradation such as shrinkage and other problems due to subsequent thermal excursions after formation and curing of the dielectric layer. In applications where there is contact with other organic chemicals and solvents, as in photolithography and cleaning processes as are conventionally employed in the art of microelectronics fabrication, the stability of the dielectric layer must be sufficient to withstand such exposure.
Although desirable for having relatively lower dielectric constant values, spin-on-polymer (SOP) dilectric materials which are employed for forming spin-on-polymer (SOP) dielectric layers in microelectronics fabrications are not without additional problems. In particular, curing of spin-on-polymer (SOP) dielectric layers by thermal annealing at an elevated temperature after conventional spin coating often results in incomplete or non-uniform stability of the resulting cured dielectric layer, particularly with respect to subsequent changes in physical or in chemical properties when the dielectric layer is exposed to additional thermal stresses and/or environmental conditions analogous to the curing conditions during operation of the device.
It is therefore towards the goal of forming within microelectronics fabrications low dielectric constant dielectric layers formed from spin-on-polymer (SOP) dielectric materials, while forming the low dielectric constant dielectric layers with attenuated shrinkage and stabilized physical and chemical properties, that the present invention is more generally directed.
Various methods and materials and associated microelectronics structures have been disclosed within the art of microelectronics fabrication for forming between and around patterned microelectronics conductor layers within microelectronics fabrications low dielectric constant dielectric layers.
For example, Mercer, in U.S. Pat. No. 4,920,005, discloses a composition of two organic polymers which upon mixing cure to form a dielectric layer useful as electrical insulation between and around conductive or semiconductive layers. One of the components is an aromatic polymer with a preponderance of a single repeat unit, and the other component is a compatible reactive material such as an acetylene, maleimide, vinyl-terminated

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