Reduction of sheet resistance of phosphorus implanted...

Details Reduction of sheet resistance of phosphorus implanted... Reduction of sheet resistance of phosphorus implanted...

2011-04-12

2011-04-12

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C257SE21343

Reexamination Certificate

active

07923359

ABSTRACT:
There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.

REFERENCES:
patent: 4933296 (1990-06-01), Parks et al.
patent: 5962896 (1999-10-01), Yabuta et al.
patent: 6465311 (2002-10-01), Shenoy
patent: 6744108 (2004-06-01), Pan

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