Reduction of reverse short channel effects by implantation...

Details Reduction of reverse short channel effects by implantation... Reduction of reverse short channel effects by implantation...

2001-11-12

2002-11-26

Thompson, Craig (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S611000, C257S616000

Reexamination Certificate

active

06486510

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor devices and specifically to reverse short channel effects occurring in semiconductor devices.
The trend of decreasing feature size in semiconductor integrated circuits has led to devices with channel lengths approaching 0.05 microns. As the effective channel length (L
eff
) decreases, however, the gate voltage at which the conductivity of the channel is inverted and conduction occurs—the threshold voltage—increases above the theoretically predicted level.
FIG. 1
shows this increase in voltage, or reverse short channel effect (RSCE), which is generally an undesirable effect. The dashed line in
FIG. 1
represents an ideal channel conductivity behavior in a gated device.
The tendency towards higher threshold voltages with decreased channel length reverses at some point, and the threshold voltage drops off dramatically. This sudden decrease in threshold voltage is referred to as the short channel effect (SCE). Conventionally, as action is taken to reduce the RSCE, the SCE worsens, which is an undesirable collateral effect.
The RSCE is generally believed to be caused in n-type metal oxide semiconductor field effect transistors (NMOSFETs) by pile-up of threshold boron at the edge of the source and drain, as well as generally uneven boron distribution across the channel region in FETs with short channels. Supplemental implantation of p-type ions in the channel region has been used to attempt to prevent the RSCE by reducing the impact of boron pile-up in the channel region.
Another technique that has been employed to reduce the RSCE in FETs is the implantation of germanium into the source and drain regions of the FET.
FIG. 2
shows a cross-section of an NFET generally at
10
, in which shallow germanium implants
22
have been incorporated into the source
18
and drain
20
regions. A p-type silicon substrate
12
comprises a gate
14
disposed on a gate oxide
15
and between sidewall spacers
16
. The source
18
and drain
20
diffusions each have shallow germanium implants
22
that are formed to prevent the RSCE.
Conventional techniques used to reduce the RSCE, however, can require additional processing steps and can cause unwanted collateral effects on the performance of the device. What is needed in the art is a method for fabricating a semiconductor device that does not suffer from RSCEs.
BRIEF SUMMARY OF THE INVENTION
The present invention is a semiconductor device comprising a semiconductor substrate, a first diffusion region disposed in said substrate, a second diffusion region disposed in said substrate, a channel region disposed between said first diffusion region and said second diffusion region, a gate oxide disposed on said semiconductor substrate over said channel region and overlapping said first diffusion region and said second diffusion region, a gate electrode disposed on said gate oxide, and a neutral dopant diffusion implant disposed throughout said substrate, said neutral dopant diffusion implant having a peak concentration below said first diffusion region and said second diffusion region.
The process for making said device comprises forming an oxide layer on a semiconductor substrate of a first conductivity type, blanket-implanting a neutral dopant into said substrate to form a neutral dopant implant, forming a gate electrode on said oxide layer, and, implanting source and drain regions into said substrate to a depth less than the depth at which a peak concentration of said germanium implant occurs.


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James R. Pfiester, Mark E. Law, and Robert W. Dutton; “Improved MOSFET Short-Channel Device Using Germanium Implantation,” IEE Election Device Letters, vol. 9, No. 7, Jul. 1988, pp. 343-346.
Kwok K. Ng, Chien-Shing Pai, William M. Mansfield, and Glenn A. Clarke; “Suppression of Hot-Carrier Degradation in SI MOSFET's by Germanium Doping,” IEE Election Device Letter, vol. 11, No. 1, Jan. 1990, pp. 45-47.
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