Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-03-21
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S303000, C438S682000, C257S607000, C257S611000, C257S768000
Reexamination Certificate
active
06376343
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices, e.g., high-density integrated circuit (“IC”) semiconductor devices exhibiting reliable, high quality, adherent, low resistance, well-aligned contacts to source, drain, and gate regions of active devices, such as MOS and CMOS transistors formed in or on a semiconductor substrate, by utilizing self-aligned, metal silicide (“salicide”) processing methodology. The present invention enjoys particular utility in the manufacture of high-density integration semiconductor devices, including multi-level devices, having design rules of 0.18 &mgr;m and below, e.g., 0.15 &mgr;m and below.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) devices necessitate design rules of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, with increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction in feature sizes, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional contact and interconnection technology, including conventional photo-lithographic, etching, and deposition techniques.
As a result of the ever-increasing demand for large-scale and ultra small-dimensioned IC devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease in the deep sub-micron range, both vertically and laterally, many problems arise, especially those caused by an increase in the sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of self-aligned, highly electrically conductive metal silicides, i.e., “salicides” (derived from Self-ALIgned-siliCIDE), has become commonplace in the manufacture of IC semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with metal silicide technology is the use of, shallow-depth source and drain extensions formed just at the edge of the gate region, while more heavily-doped source and drain regions, to which ohmic contact is to be provided, are laterally displaced away from the gate by provision of sidewall spacers on opposing sides of the gate electrode. Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon (Si), but does not react with silicon oxides, nitrides, or oxynitrides under normal processing conditions. Metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each of which forms very low resistivity phases with Si, e.g., PtSi
2
, TiSi
2
, NiSi, and CoSi
2
. In practice, the metal is deposited in a uniform thickness over all exposed surface features of a Si wafer, preferably by means of physical vapor deposition (“PVD”) process, e.g., sputtering from an ultra-pure target utilizing an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed both after gate etch and after source/drain formation. After deposition, the metal layer blankets the top surface of the gate electrode, typically formed of a heavily-doped polysilicon, the silicon oxide, nitride, or oxynitride sidewall spacers on the opposing side surfaces of the gate electrode, the silicon oxide isolation regions formed in the Si substrate between adjacent active device regions, and the exposed surfaces of the substrate where the source and drain regions are to be formed or will subsequently be formed. As a result of thermal processing, e.g., a rapid thermal annealing (“RTA”), the metal layer reacts with underlying Si to form electrically conductive metal silicide layer portions on the top surface of the polysilicon gate electrode and on the exposed surfaces of the substrate where source and drain regions are or will be formed. Unreacted portions of the metal layer, e.g., on the silicon oxide, nitride, or oxynitride sidewall spacers and the silicon oxide isolation regions, are then removed, as by a wet chemical etching process selective to the metal silicide portions. In some instances, e.g., with Co, a first RTA step may be performed at a relatively lower temperature in order to form first-phase CoSi, which is then subjected to a second RTA step performed at a relatively high temperature to convert the first-phase CoSi to second-phase, lower resistivity CoSi
2
.
A number of different techniques and fabrication processes have been either proposed or utilized for forming MOS transistors and/or CMOS devices according to salicide methodology. Referring to FIGS.
1
(A)-
1
(I), shown therein, for illustrative purposes only, is an example of a typical salicide-based process according to conventional processing technology. In a preliminary step, shown in FIG.
1
(A), a silicon (Si) or Si-based substrate
102
, typically a monocrystalline Si wafer of one conductivity type (p or n) or comprising a well region of one conductivity type formed therein, is processed, as by conventional techniques such as formation of field oxide regions, local oxidation of silicon (“LOCOS”), shallow trench isolation (“STI”), etc., to define a plurality of electrically separated regions. In the illustrated embodiment, shallow isolation trenches
216
(only one is shown for illustrative simplicity) are formed in a surface portion of substrate
102
, as by isotropic etching utilizing wet chemical etching techniques or by anisotropic etching utilizing dry etching techniques, e.g., reactive plasma etching. Trenches
216
are then filled with an oxide
218
layer, such that an edge
220
of the oxide
218
contacts the substrate
102
at locations where doped regions will subsequently be formed within the substrate
102
. (Trench
216
and oxide layer
218
are not shown in the following drawing figures for illustrative simplicity).
Referring now to FIG.
1
(B), a thin gate oxide (insulator) layer
104
, typically a silicon oxide layer about 15-50 Å thick, is formed on the upper surface of substrate
102
, e.g., by thermal oxidation at temperatures of from about 700 to about 1,000° C. in an oxidizing atmosphere. After formation of the gate oxide layer
104
, a blanket layer of undoped polysilicon
106
is deposited on the gate oxide layer
104
, for example, by low pressure chemical vapor deposition (“LPCVD”). If desired, polysilicon layer
106
can be treated to retard diffusion of boron (B) atoms therethrough, as by implantation with nitrogen (N
2
) ions, symbolically indicated in the figure by arrows
160
.
Adverting to FIG.
1
(C), a continuous photoresist layer
110
is then deposited on the polysilicon layer
106
, and the photoresist layer
110
is selectively irradiated utilizing photolithographic masking techniques and developed, followed by removal of the selectively irradiated portions thereof to expose portions of the polysilicon layer
106
which are to be removed to define a gate electrode. As shown in FIG.
1
(D), the exposed portions of polysilicon layer
106
and the respective underlying portions of the thin gate oxide layer
104
are removed, as by anisotropic etching, to form polysilicon gate electrode
112
having vertically opposed sidewalls or edges
114
,
116
.
With reference to FIG.
1
(E), the remaining portion of the photoresist layer
110
is then stripped from the upper surface of the polysilicon gate electrode
112
and a pair of shallow-depth, source and drain extension regions
130
,
132
are formed in substrate
102
by an ion implantation
128
(“extension implant”) process, utilizing the polysilicon gate electrode
112
as an implantation mask. Source and drain extension regions
130
,
132
thus are formed in a self-aligned manner and extend within the substrate
102
to immediately adjacent the edges of sidewalls
Besser Paul R.
Buynoski Matthew S.
Xiang Qi
Advanced Micro Devices , Inc.
Bowers Charles
Smoot Stephen W.
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