Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-04-18
2002-10-01
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S407000, C438S423000, C438S672000, C438S690000
Reexamination Certificate
active
06458634
ABSTRACT:
DETAILED DESCRIPTION OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a method of substantially reducing charge build-up on silicon-on-insulator (SOI) devices during the fabrication of probe contacts on an interconnect structure in which SOI devices are embedded.
2. Background of the Invention
Focused ion beam (FIB) is a useful tool in preparing a device for characterization and/or diagnostic testing by fabricating contact pads at nodes of interest. Present FIB techniques can induce excessive charge on an SOI device, which the SOI device cannot tolerate due to the floating body nature of the SOI device. The excessive charge may induce temporary or permanent damage of the SOI device (especially of concern is the gate dielectric region of the device). Excessive charge induced by the FIB process may also destroy the very defect under investigation
FIG. 1
identifies a typical cross-section of semiconductor structure
10
after prior art FIB processing. The semiconductor structure, which includes SOI devices (referred to as active devices in FIG.
1
), has been planarized to the desired interconnect level. Reference numeral
12
represents the wiring region of the interconnect level and it represents the node of contact. Local oxide
14
is then deposited in the region where FIB pads
16
are to be formed. Next, a FIB tool is used to drill a hole in the local oxide to the desired node, i.e., point of contact. Finally, a conductive metal such as Al or Cu is deposited in the hole and atop of local oxide
14
to form pad
16
and via
18
to the node, i.e., wiring region
12
of the interconnect level of interest. During the drilling process, the FIB tool generates excessive charge. This excessive charge is coupled to the contact point when the oxide is removed during drilling. An underlying SOI device, due to its nature, cannot dissipate the excessive charge.
FIG. 2
is a top-down view of the structure shown in FIG.
1
.
In view of the excessive charge problem mentioned above with prior art FIB processes, there is a need for developing a new and improved method which is capable of sufficiently dissipating charge away from SOI devices during the formation of probe contacts.
SUMMARY OF THE INVENTION
The present invention provides a method which is capable of substantially reducing induced charge in SOI devices during a drilling step such as FIB. Specifically, the inventive method comprises the steps of:
(a) depositing a dielectric material on a surface of a semiconductor structure, said structure including at least silicon-on-insulator (SOI) devices;
(b) depositing a first conductive material on said dielectric material;
(c) drilling holes through said first conductive material and said dielectric material;
(d) filling said holes with a second conductive material; and
(e) selectively removing portions of said first conductive material, stopping on said dielectric material.
In one embodiment of the present invention, the first conductive material is connected to a ground potential prior to and during drilling. In another embodiment of the present invention, an alignment process may be coupled with the drilling step. In yet another embodiment of the present invention, a dry etching step precedes the drilling step to enlarge the holes drilled into the first conductive material and the dielectric material.
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Scully Scott Murphy & Presser
Smoot Stephen W.
Walsh Robert A.
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