Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-05-16
2006-05-16
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230010, C365S230030, C365S244000, C711S200000, C711S202000, C714S017000, C714S038110, C714S757000, C714S766000
Reexamination Certificate
active
07046560
ABSTRACT:
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.
REFERENCES:
patent: 5281868 (1994-01-01), Morgan et al.
patent: 5574689 (1996-11-01), Morgan et al.
patent: 6026505 (2000-02-01), Hedberg et al.
patent: 6144593 (2000-11-01), Cowles et al.
patent: 6154854 (2000-11-01), Stallmo
U.S. Appl. No. 10/862,284, filed Jun. 7, 2004.
Ayyapureddi Sujeet V.
Seeram Vasu
Fish & Neave IP Group Ropes & Gray LLP
Micro)n Technology, Inc.
Pham Ly Duy
Zarabian Amir
LandOfFree
Reduction of fusible links and associated circuitry on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduction of fusible links and associated circuitry on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduction of fusible links and associated circuitry on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3580782