Reduction of contact size utilizing formation of spacer material

Details Reduction of contact size utilizing formation of spacer material Reduction of contact size utilizing formation of spacer material

1997-02-06

1999-08-03

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438692, 257752, 257775, H01L 2100

Patent

active

059324910

ABSTRACT:
A method for forming a sidewall aligned contact structure without a hardmask layer. A semiconductor region is provided having an active area at an upper surface. An insulating layer is formed having an upper surface over the active area. Using a photo-patterned organic mask, a gross contact opening is etched in the insulating layer over the active area. The gross contact opening extends downward from the upper surface and partially through the insulating layer. A conformal layer of material is deposited at low temperature over the patterned mask as well as sidewalls and a bottom surface of the gross contact opening The conformal layer comprises a material that is differentially etchable with respect to the photomask and preferably etches similarly to the insulating layer. A portion of the insulating layer at the base of the gross contact opening is exposed. A contact opining is formed in the exposed portion of the insulating layer using the remaining conformal layer as a mask.

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H. Sakai et al., "A Trench Isolation Technology For High-Speed And Low-Power Dissipation Bipolar LSI's," Semiconductor Research Center, Japan, pp. 17-18.
S. Kimura et al., "A New Stacked Capacitor DRAM Cell Characterized By A Storage Capacitor On A Bit-Line Structure," Central Research Laboratory, Japan, 1988, IEEE, pp. 596-599.

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