Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2002-04-04
2004-08-03
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S005000, C711S157000, C711S207000, C711S217000, C711S218000
Reexamination Certificate
active
06772271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus having a main memory and a plurality of memory banks.
2. Description of the Related Art
One conventional data processing apparatus will be described below with reference to
FIGS. 1 and 2
of the accompanying drawings. As shown in
FIG. 1
, the data processing apparatus has main memory
101
, n memory banks
102
1
, through
102
n
, CPU (Central Processing Unit)
103
, and register circuit
104
.
Main memory
101
has a number of successive memory spaces each having a series of main addresses “000”, “001”, . . . , “010” set thereto. Memory banks
102
1
through
102
n
also have a plurality of successive memory spaces, and the memory spaces of each memory bank have common successive bank addresses “011”, “012”, . . . , “100” set thereto. CPU
103
is connected to main memory
101
and memory banks
102
1
through
102
n
by address bus
105
and a data bus (not shown), and reads data stored in main memory
101
successively in the order of the main addresses and data stored in memory banks
102
1
through
102
n
successively in the order of the bank addresses. Register circuit
104
is connected to main memory
101
, memory banks
102
1
through
102
n
, and CPU
103
, and is controlled by CPU
103
to store the bank number of one of memory banks
102
1
through
102
n
.
In the conventional data processing apparatus, a series of computer program instructions for CPU
103
are stored in main memory
101
and memory banks
102
1
through
102
n
. CPU
103
reads the computer program instructions and executes data processing according to the read computer program instructions.
As shown in
FIG. 2
of the accompanying drawings, main memory
101
stores, at arbitrary main addresses, a first bank switching instruction, a second bank switching instruction, . . . , an nth bank switching instruction for branching readout destinations for CPU
103
to respective memory banks
102
1
,
102
2
, . . . ,
102
n
. Memory banks
102
1
,
102
2
, . . . ,
102
n
store, at respective final bank addresses, a first main return instruction, a second main return instruction, . . . , an nth main return instruction for branching readout destinations for CPU
103
to respective main addresses next to those main addresses where the first bank switching instruction, the second bank switching instruction, . . . , the nth bank switching instruction are stored in main memory
101
.
When CPU
103
reads the series of computer program instructions from the main memory
101
and memory banks
102
1
through
102
n
, since stored data in main memory
101
are successively read from the first main address, the bank switching instructions are read from certain main addresses.
In the illustrated conventional data processing apparatus, the first bank switching instruction which is read first designates the first bank address in memory bank
102
1
, and hence the readout destination for CPU
103
is branched to the first bank address in memory bank
102
1
. At this time, CPU
103
stores the memory bank number “1” corresponding to the first bank switching instruction in register circuit
104
. Therefore, only memory bank
102
1
, becomes valid, and memory banks
102
2
through
102
n
become invalid. As a result, CPU
103
reads stored data in memory bank
102
1
, successively from its bank addresses beginning with the first bank address until finally it reads the main return instruction. Since the main return instruction stored in memory bank
102
1
, designates the main address next to the main address where the first bank switching instruction is stored in main memory
101
, the readout destination for CPU
103
becomes the main address next to the main address where the first bank switching instruction is stored in main memory
101
.
Similarly, CPU
103
reads data from main memory
101
, and each time CPU
103
reads a bank switching instruction, it reads stored data in a corresponding memory bank. When the readout of data from memory bank
102
n
, is completed, the processing returns to the readout of data from main memory
101
.
The conventional data processing apparatus use common bank addresses shared by memory banks
102
1
through
102
n
. When CPU
103
stores a memory bank number corresponding to a bank switching instruction in register circuit
104
, plural memory banks
102
become valid one at a time. Therefore, a small number of bank addresses can be assigned to many memory spaces.
However, since it is necessary to store the first through nth bank switching instructions which designate first through nth memory banks memory banks
102
1
through
102
n
, respectively, in main memory
101
, some of the memory spaces in main memory
101
are consumed for storing these bank switching instructions.
Furthermore, the final bank addresses of first through nth memory banks memory banks
102
1
through
102
n
are required to set therein the first through nth main return instructions which designate the main addresses next to the main addresses where the first through nth bank switching instructions are stored in main memory
101
. The process of setting the first through nth main return instructions in the final bank addresses is complex.
In addition, main memory
101
is unable to store considerably long successive data therein because the first through nth bank switching instructions are stored at arbitrary main addresses.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data processing apparatus which minimizes the consumption in a main memory of memory spaces for bank switching instructions, is not required to set main return instructions inherent in respective memory banks, and is capable of storing considerably long successive data in the main memory.
According to a first aspect of the present invention, a data processing apparatus has a main memory, first through nth memory banks, a data processing circuit, and a bank switching means.
The main memory has a plurality of successive memory spaces each with a series of main addresses set thereto and stores in an arbitrary memory space thereof a bank switching instruction which designates a first bank address of the first memory bank. The first through nth memory banks have a plurality of successive memory spaces with a series of bank addresses set commonly thereto, and the first through (n-1)th memory banks having virtual spaces where no stored data is present in respective final bank addresses thereof. The nth memory bank stores in the memory space represented by the final bank address thereof a main return instruction which designates a particular main address of the main memory.
The data processing circuit reads stored data in the memory spaces successively from the main addresses beginning with a head address. The data processing circuit switches the readout destination therefor to the head bank address of the first memory bank and reads data successively from the first memory bank beginning with the head address. When the readout destination in the first memory bank reaches the bank address of the virtual space, the readout destination is switched to the second memory bank by the bank switching means, and the data processing circuit reads data successively from the second memory bank beginning with the head address. The above operation is repeated until the readout destination is switched to the nth memory bank. When the main return instruction is read from the final bank address of the nth memory bank, the readout destination returns to a particular main address of the main memory. Having read all the stored data in the memory banks, the data processing circuit reads data subsequent to the particular main address of the main memory.
According to a second aspect of the present invention, the main memory stores in an arbitrary memory space thereof a bank switching instruction which designates a particular bank address of the first memory bank, the first through (n-1)th memory banks have virtual spaces where
Sparks Donald
Truong Bao
LandOfFree
Reduction of bank switching instructions in main memory of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduction of bank switching instructions in main memory of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduction of bank switching instructions in main memory of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3342991