Reducing two variables in alternate clock cycles during data tra

Details Reducing two variables in alternate clock cycles during data tra Reducing two variables in alternate clock cycles during data tra

1998-06-09

2000-03-21

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

711131, 711 5, 358 114, 345505, G06F 1200

Patent

active

060413697

ABSTRACT:
An improved apparatus and method for monitoring and controlling when a data phase in a burst transmission of data is about to end. The apparatus described interleaves dual adder circuits such that each dual adder circuit has more time to process incoming data. Distribution of the processing allows slower, lower cost components to be used in high speed applications. The described apparatus and method are particularly useful in peripheral component interconnect applications.

REFERENCES:
patent: 5539891 (1996-07-01), Childers et al.
patent: 5557734 (1996-09-01), Wilson
patent: 5581669 (1996-12-01), Voth
patent: 5732241 (1998-03-01), Chan
patent: 5768622 (1998-06-01), Lory et al.
patent: 5832302 (1998-11-01), Watkins
patent: 5918072 (1999-06-01), Bhattacharya

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