Reducing transitions on address buses using...

Details Reducing transitions on address buses using... Reducing transitions on address buses using...

2005-06-14

2005-06-14

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S213000, C711S220000, C712S233000, C712S237000

Reexamination Certificate

active

06907511

ABSTRACT:
An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.

REFERENCES:
patent: 4729092 (1988-03-01), Lupton
patent: 4860197 (1989-08-01), Langendorf et al.
patent: 4905141 (1990-02-01), Brenza
patent: 5283873 (1994-02-01), Steely et al.
patent: 5581719 (1996-12-01), Steely et al.
patent: 5933860 (1999-08-01), Emer et al.
patent: 5978908 (1999-11-01), Cumming et al.
patent: 6167509 (2000-12-01), Sites et al.
patent: 6289444 (2001-09-01), Nair
L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems,” IEEE7th Great Lakes Symposium on VLSI, Urbana, IL, pp. 77-82, Mar. 1997.
W. Fornaciari, M. Polentarutti, D. Sciuto, C. Silvano, “Power Optimization of System-Level Address Buses Based on Software Profiling,”CODES, pp. 29-33, 2000.
L. Benini, G. De Micheli, E. Macii, M. Poncono, S. Quer, “System-Level Power Optimization of Special Purpose Applications: The Beach Solution,”IEEE Symposium on Low Power Electronics and Design, pp. 24-29, Aug. 1997.
P. Panda, N. Dutt, “Reducing Address Bus Transitions for Low Power Memory Mapping,” European Design and Test Conference, pp. 63-67, Mar. 1996.
E. Musoll, T. Lang, J. Cortadella, “Exploiting the locality of memory references to reduce the address bus energy,” Proceedings of International Symposium on Low Power Electronics and Design, Monterey, CA, pp. 202-207, Aug. 1997.
M.R. Stan, W.P. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Transactions on VLSI Systems, vol. 3, No .1, Mar. 1995.
M. Mamidipaka, D. Hirschberg, N. Dutt, “Low Power Address Encoding using Self-Organizing Lists,” International Symposium on Low Power Electronics and Design, Aug. 2001.
S. Ramprasad, N. Shanbhag, I. Hajj, “A Coding Framework for Low Power Address and Data Busses,” IEEE Transactions on VLSI Systems, vol. 7, No. 2, Jun. 1999.
Y. Aghaghiri, F. Fallah, M. Pedram, “Irredundant Address Bus Encoding for Low Power,” International Symposium on Low Power Electronics and Design, pp. 182-187, Aug. 2001.
L. Macchiarulo, E. Macii, M. Poncino, “Low-energy for Deep-submicron Address Buses,” International Symposium on Low Power Electronics and Design, pp. 176-181, Aug. 2001.
S. Iman, M. Pedram, “POSE: Power Optimization and Synthesis Environment,” Proc. of 33rd Design Automation Conference, pp. 21-26, Jun. 1996.
P.P. Sotiriadis, A. Wang, A. Chandrakasan, “Transition Pattern Coding: An approach to reduce Energy in Interconnect”.
N. Chang, K. Kim, J. Cho, “Bus Encoding for Low-Power High-Performance Memory Systems,” 37th Conference on Design Automation, Jun. 2000.
P. Chang, E. Hao, Y.N. Patt, “Target Prediction for Indirect Jumps,” 24th International Symposium on Computer Architecture, Jun. 1997.
J.E. Smith, “A Study of Branch Prediction Strategies,” 8th International Sympoisum on Computer Architecture, pp. 202-215, May 1981.
Y. Shin, S.I. Chae, K. Choi, “Partial Bus-Invert Coding for Power Optimization of System Level Bus,” ISLPED '98, pp. 127-127, Aug. 1998.
M.R. Stan, P. Burleson, “Low-Power Encodings for Global Communication in CMOS VLSI,” IEEE Transactions on VLSI Systems, vol. 5, No. 4, Dec. 1997.
L. Benini, G. de Micheli, E. Macii, D. Sciuto, C. Silvano, “Address Bus Encoding Techniques for System-Level Power Optimization,” DATE-98, pp. 861-866, Feb. 1998.
S. Komatsu, M. Ikeda, K. Asada, “Low Power Chip Interface based on Bus Data Encoding with Adaptive Code-book Method”.

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