Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2008-07-20
2010-11-16
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S239000, C712S240000
Reexamination Certificate
active
07836287
ABSTRACT:
A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.
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Office Action for U.S. Appl. No. 12/176,386 dated May 11, 2010.
Doing Richard William
Olsson Brett
Tsuchiya Kenichi
Alrobaye Idriss N
Chan Eddie P
International Business Machines - Corporation
Voight, Jr. Robert A.
Winstead P.C.
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