Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2005-04-19
2008-10-14
Dollinger, Tonia L. M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S238000
Reexamination Certificate
active
07437543
ABSTRACT:
A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.
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Doing Richard William
Olsson Brett
Tsuchiya Kenichi
Cockburn Joscelyn G.
Dollinger Tonia L. M.
International Business Machines - Corporation
Voigt, Jr. Robert A.
Winstead PC
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