Reducing tester channels for high pinout integrated circuits

Details Reducing tester channels for high pinout integrated circuits Reducing tester channels for high pinout integrated circuits

2005-11-29

2005-11-29

Beausoliel, Robert (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S027000

Reexamination Certificate

active

06971045

ABSTRACT:
An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.

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