Reducing tag-ram accesses and accelerating cache operation...

Details Reducing tag-ram accesses and accelerating cache operation... Reducing tag-ram accesses and accelerating cache operation...

2006-01-03

2006-01-03

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

06983346

ABSTRACT:
This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line.

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