Reducing sub-threshold leakage in a memory array

Details Reducing sub-threshold leakage in a memory array Reducing sub-threshold leakage in a memory array

2005-08-23

2005-08-23

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C356S072000

Reexamination Certificate

active

06934181

ABSTRACT:
A method and memory array for reducing sub-threshold leakage in a memory array. A memory array may include a plurality of rows where each row may include one or more groups of cells. Within each group of cells, each cell may be coupled to a ground path and to a power path. A device, e.g., n-type transistor, p-type transistor, may be coupled to either the ground or power path in each group of cells thereby permitting the passing of the sub-threshold leakage from those cells in that group through the device. Consequently, the sub-threshold leakage in the memory array may be reduced.

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