Reducing stress in a flip chip assembly

Details Reducing stress in a flip chip assembly Reducing stress in a flip chip assembly

2007-06-11

2010-06-01

Zarneke, David A (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257SE23021

Reexamination Certificate

active

07727805

ABSTRACT:
In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to reflow the alloy material to form a joint therebetween. Other embodiments are described and claimed.

REFERENCES:
patent: 5874043 (1999-02-01), Sarkhel et al.
patent: 6548898 (2003-04-01), Matsuki et al.
patent: 6879041 (2005-04-01), Yamamoto et al.
patent: 7332821 (2008-02-01), Bernier et al.
patent: 7547577 (2009-06-01), Card et al.
patent: 2002/0089067 (2002-07-01), Crane et al.
U.S. Appl. No. 11/617,819, filed Dec. 29, 2006, entitled “Flux Overspray Reduction Apparatus, Systems, And Methods,” by James Patrick Mellody, et al.

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