Reducing short circuit power in CMOS inverter circuits

Details Reducing short circuit power in CMOS inverter circuits Reducing short circuit power in CMOS inverter circuits

2002-07-31

2004-02-03

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S121000

Reexamination Certificate

active

06686773

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits, and more specifically to a method and apparatus for reducing short circuit power consumed in CMOS inverter circuits.


REFERENCES:
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patent: 5111076 (1992-05-01), Tarng
patent: 6097237 (2000-08-01), Singh
patent: 04263514 (1992-09-01), None
K. Y. Khoo and A. N. Wilson Jr.; Entitled: “Low Power CMOS Clock Buffer”; Proc. Int. Symp. Circuits and Systems; vol. 4, 1994; pp. 355-358; (4 Pages).
Harry. J. M. Veendrick; Entitled: “Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits”; IEEE, Journal of Solid-State Circuit; Aug. 1984; pp. 468-473; (6 Pages).
H.-Y. Huang and Y.-H. Chu; Entitled: “Feedback-Controlled Split-Path CMOS Buffer”; Proc. Int. Symp. Circuits ad Systems; vol. 4, 1996; pp. 300-303; (4 Pages).
K.-H. Cheng, W.-B. Yang and H.-Y. Huang; Entitled: “The Charge—Transfer Feedback-Controlled Split-Path CMOS Buffer”; IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing vol. 46, No. 3, Mar. 1999; pp. 346-348; (3 Pages).
Changsik Yoo; Entitled: “A CMOS Buffer without Short-Circuit Power Consumption”; IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing; vol. 47 No. 9, Sep. 2000; pp. 935-937; (3 Pages).

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