Reducing power consumption in a sequential cache

Details Reducing power consumption in a sequential cache Reducing power consumption in a sequential cache

2004-12-29

2008-11-25

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S128000, C713S300000, C713S324000

Reexamination Certificate

active

07457917

ABSTRACT:
In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.

REFERENCES:
patent: 6018786 (2000-01-01), Krick et al.
patent: 6021461 (2000-02-01), Dhong et al.
patent: 6535959 (2003-03-01), Ramprasad et al.
patent: 6578138 (2003-06-01), Kyler et al.
patent: 2002/0129201 (2002-09-01), Maiyuran et al.
Koopman, Phillip, Main Memory Architecture,Oct. 1998,Carnegie Mellon,pp. 3,6.
Rosner, R., A. Mendelson and R. Ronen.Filtering Techniques to Improve Trace-Cache Efficiency. Sept. 2001. pp. 1-12. (http://www.intel.com/research/mrl/Library/trace—filtering.pdf).

Affiliated with

Also associated with

Rating

Reducing power consumption in a sequential cache does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reducing power consumption in a sequential cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing power consumption in a sequential cache will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4023808