Reducing leakage power in low power mode

Details Reducing leakage power in low power mode Reducing leakage power in low power mode

2008-02-20

2010-10-05

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C327S201000, C365S227000, C365S229000, C713S320000, C326S040000

Reexamination Certificate

active

07808273

ABSTRACT:
Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal.

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