Reducing leakage current in memory cells

Details Reducing leakage current in memory cells Reducing leakage current in memory cells

2001-05-14

2003-09-30

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S063000

Reexamination Certificate

active

06628551

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to memory cells having improved retention time.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
FIG. 1
shows a conventional SRAM cell
101
. The SRAM cell comprises first and second transistors
110
and
120
coupled to a latch
130
, which stores a bit of information. One transistor is coupled to a bit line
140
and the other is coupled to a bit line complement
141
while the gates are coupled to a word line
135
. The latch includes first and second inverters
133
and
134
, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime due to current leakage. To prevent the charge from dissipateing below an undefined logic level (logic 0 or 1), the memory cell must be refreshed. Typically, refreshing of memory cells interrupt the normal operation, thus adversely impacting the performance of the IC.
As evidenced from the above discussion, it is desirable to provide a memory cell with improved charge retention to decrease the refresh frequently.
SUMMARY OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to improving retention time in memory cells. In one embodiment, the memory cell comprises first and second access transistors coupled to respective first and second terminals of a storage transistor. The access transistors are high gate threshold voltage transistors. Providing access transistors having a high gate threshold voltage reduces leakage current through their channels. In one embodiment, the gate threshold voltages of the access transistors are about 0.1-0.4V higher than typical transistors.


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