Reducing latency, when accessing task priority levels

Details Reducing latency, when accessing task priority levels Reducing latency, when accessing task priority levels

2003-09-24

2008-09-16

An, Meng-Ai (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Task management or control

C718S102000, C718S103000, C710S049000, C710S260000, C710S262000, C710S264000, C710S266000

Reexamination Certificate

active

07426728

ABSTRACT:
One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt mask value is written to the TPR. In addition, the interrupt mask value is also written into a shadow copy of the TPR. The shadow copy is written each time that the TPR is written. Another embodiment disclosed relates to a method of reducing a latency to read a TPR of an IPF type microprocessor. When a command is received to read an interrupt mask value from the TPR, the interrupt mask value is read from the shadow copy at a memory location, instead of from the task priority register itself.

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