Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-07-21
2002-11-12
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C710S316000, C370S386000
Reexamination Certificate
active
06480921
ABSTRACT:
BACKGROUND
The present specification generally relates to a bus system and particularly to a high-speed data transfer system.
A bus is an electrical channel that interconnects two or more devices. The bus channel includes a number of wires that can perform at least one of data transfer, timing and synchronization, and bus arbitration. Digital buses inside a computer carry either data or addresses of memory cells. However, the digital bus encounters a scaling problem as the number of connections to the bus increases.
Digital imaging devices, such as active pixel sensor (APS) cameras, include many image sensors arranged into arrays of columns and rows. Each image sensor collects electrical charge when exposed to light. Control signals are provided to the image sensors to enable the sensors to periodically transfer the collected charges to analog-to-digital converters (ADCs). The converted digital data are then stored in the column-parallel ADC registers.
A single serial bus is used to carry column-parallel sensor data stored in the ADC registers to the output port. For an image sensor with an array of 1280×720 pixels, there are 1280 columns per row and can be as many connections to the serial bus. Therefore, the internal bus speed, and hence the readout rate, must be very high in order to transfer an entire array of pixel data or frame in less than {fraction (1/60)} of a second.
SUMMARY
The inventors noticed that by replacing the single serial bus-with several parallel buses and sequentially directing data placed on the parallel buses to output ports at high speed, internal bus speed can be reduced without reducing the readout rate. Furthermore, the addition of parallel buses enables the number of connections to each bus to be reduced. This can reduce parasitic capacitance and lower the input loads on the bus lines.
In one aspect, the present specification involves transportation of data by a bus system having input ports and output ports. The bus system includes bus lines, switching elements, and a sequencing element.
The bus lines channel data from the input ports to the output ports. The switching elements are configured to place data from the input ports onto the bus lines. Each of the switching elements enable part of a group of data to be placed on each of the bus lines simultaneously. The sequencing element selects a part, e.g. predetermined number of the group of data on the bus lines, and sequentially directs the selected number of data to the output ports at different points in time.
The bus system also includes buffering elements connected to the bus lines and the sequencing element. The buffering elements buffer the current data placed on the bus lines and allow the switching elements to place the next group of data onto the bus lines while the sequencing element is directing the previous group of data to the output ports.
In some embodiments, eight bus lines channel data from the input ports to the output ports. In addition, eight switching elements allow eight data packets from the input ports to be placed simultaneously on the eight bus lines. The sequencing element includes two multiplexers. Each multiplexer is coupled to four of the eight bus lines and has an output port. The multiplexer is configured to select data on one of the four bus lines. It sequentially directs the selected data to the output port at different points in time.
In another embodiment, there are sixteen bus lines channeling data from the input ports to the output ports. In addition, sixteen switching elements allow sixteen data packets from the input ports to be placed simultaneously on the sixteen bus lines. The sequencing element selects the data on four bus lines during one time slot to sequentially direct the selected data to the four output ports.
In another aspect, an active pixel sensor (APS) system having output ports is disclosed. The APS system includes a pixel sensor array, a row-select element, an array of ADC registers, and a bus system.
The pixel sensor array is arranged in an array of rows and columns. The array is configured to form an electrical representation of an image being sensed. The row-select element is configured to select a row of pixel sensors. The array of ADC registers converts electrical charges sensed by the row of pixel sensors to digital pixel data and stores them in the registers. The bus system is configured to transfer pixel data from the array of ADC registers to the output ports. The APS system also includes a timing and control unit configured to generate timing and control signals that select appropriate pixel data and transfer the data to the output ports.
In another aspect, an APS camera system for converting an array of pixel data to a visual image is disclosed. The camera system includes all of the elements in the APS system and an image display device. The display device arranges the pixel data from the bus output ports in sequential order of rows to display the visual image on the display screen.
In a further aspect, a microcomputer system is disclosed. The system includes a central processing unit, a memory device, a bus system, and a peripheral devices. The central processing unit is configured to control and process various data. The memory device is connected to the central processing unit and is configured to supply the central processing unit with processing data. The bus system transfers the processed data from the central processing unit to bus output ports. The peripheral devices transfer the processed data from the bus, output ports to the peripheral devices for various different operations.
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other embodiments and advantages will become apparent from the following description and drawings, and from the claims.
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Mansoorian Barmak
Panicacci Roger
Yee Scott
Micro)n Technology, Inc.
Ray Gopal C.
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