Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
1999-05-26
2001-06-05
Mai, Son (Department: 2818)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S027000, C326S083000, C326S087000, C327S384000
Reexamination Certificate
active
06242941
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits and more specifically to techniques and circuitry for reducing or preventing output noise for integrated circuits.
Integrated circuits (ICs) or “chips” are the building blocks of electronic systems. Electronics are used in many applications such as computers, networking, telecommunications, electronic commerce, and the internet. Some examples of electronic systems include computers, workstations, servers, telephone networks, automotive electronic ignition, network, and many others. In a system, there are many potential sources of noise. As an example, an integrated circuit generates noise when its outputs switch. Even more noise is generated when many outputs of one or more integrated circuits switch at the same time. There are many other sources of noise such as cross-coupling noise from signals propagating through the traces of a printed circuit (PC) board, RF noise or interference, or poor grounding.
It is desirable to minimize the amount of noise generated in a system. Depending on the severity, electronic noise may lead to logic errors in a system or even worse, cause the entire system to stop functioning. For example, the noise may lead to errors when handling an electronic commerce transaction. The noise may cause a computer system to crash. The noise from one integrated circuit may cause another integrated circuit in the system to malfunction.
As can be appreciated, there is a need for techniques and circuitry to reduce or prevent the noise in an integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides techniques and circuitry for operating an integrated circuit to reduce noise when switching output circuits from a programming mode to a user mode. An integrated circuit such as a programmable integrated circuit is configurable in the programming mode with user configuration data. In the user or normal mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output of the integrated circuit will switch to its user mode value. In the present invention, the outputs are released to their user mode values not all at the same time in order to minimize switching noise. In a particular implementation, the outputs of the integrated circuit are individually and sequentially returned to their user mode values one at a time. There is a delay period between one output circuit returning to its user mode and another output circuit.
One embodiment of the present invention is a method of operating an integrated circuit where in a programming mode, the I/O pins of the integrated circuit in a user-defined or high impedance state. The I/O pins are kept in the user-defined or high impedance state when exiting the programming mode. Each I/O pin of the I/O pins is released for user mode operation. There is a delay period between the release of each I/O pin. User mode operation is permitted after the plurality of I/O pins is released. Furthermore, an output driver driving each I/O pin may have a slow slew rate mode, and when switching from the programming mode to the user mode operation, the output driver drives its pin to its user mode value using the slow slew rate mode. User mode operation is permitted after releasing the output drivers coupled to the I/O pins to a user-defined slew rate mode. In the programming mode, when each I/O pin tristates or in a high impedance state, there may be a leaker device to hold the pad at a logic high state.
In another embodiment, the present invention is an integrated circuit including a first output circuit to drive a first I/O pin, and a second output circuit to drive a second I/O pin. A delay element is connected between the first and second output circuit. When exiting a programming mode of the integrated circuit, the second output circuit is released to its user mode state after the first output circuit is released to its user mode state after a delay time. This delay time is determined by the delay element. In the programming mode, the first and second output circuits may provide a high impedance or user-defined state at the first and second I/O pins. Noise at the first I/O pin and second I/O pin is reduced by releasing the first and second output circuits at different times.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
REFERENCES:
patent: 4879688 (1989-11-01), Turner et al.
patent: 5229657 (1993-07-01), Rackley
patent: 5764074 (1998-06-01), Wykes et al.
patent: 6087870 (2000-07-01), Sakamoto
Bielby Robert R. N.
Costello John C.
Fiester Mark W.
Rangasayee Krishna
Vest W. Bradley
Altera Corporation
Mai Son
Townsend and Townsend / and Crew LLP
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