Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2008-06-10
2008-06-10
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S758000, C714S780000, C714S800000
Reexamination Certificate
active
07386756
ABSTRACT:
A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
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Emer Joel S.
Mukherjee Shubhendu S.
Reinhardt Steven K.
Weaver Christopher T.
Baderman Scott
Intel Corporation
Schell Joseph
Trop Pruner & Hu P.C.
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