Reducing extrinsic base-collector capacitance

Details Reducing extrinsic base-collector capacitance Reducing extrinsic base-collector capacitance

1994-08-03

1996-06-11

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

257623, 257624, 257593, 257586, H01L 310328, H01L 31109, H01L 2906

Patent

active

055258182

ABSTRACT:
This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semi-conducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

REFERENCES:
patent: 4825265 (1989-04-01), Lunardi et al.
patent: 4914489 (1990-04-01), Awano
patent: 4967252 (1990-10-01), Awano
patent: 5070028 (1991-12-01), Tews et al.
patent: 5124270 (1992-06-01), Morizuka

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