Reducing data hazards in pipelined processors to provide...

Details Reducing data hazards in pipelined processors to provide... Reducing data hazards in pipelined processors to provide...

2007-04-03

2007-04-03

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S213000

Reexamination Certificate

active

10125331

ABSTRACT:
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.

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