Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-10-30
2007-10-30
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S300000, C713S501000, C713S600000, C713S320000
Reexamination Certificate
active
10394256
ABSTRACT:
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.
REFERENCES:
patent: 5021679 (1991-06-01), Fairbanks et al.
patent: 5153535 (1992-10-01), Fairbanks et al.
patent: 5307003 (1994-04-01), Fairbanks et al.
patent: 5404547 (1995-04-01), Diamantstein et al.
patent: 5537581 (1996-07-01), Conary et al.
patent: 5627412 (1997-05-01), Beard
patent: 5752011 (1998-05-01), Thomas et al.
patent: 5974557 (1999-10-01), Thomas et al.
patent: 6209052 (2001-03-01), Chin et al.
patent: 6216235 (2001-04-01), Thomas et al.
patent: 6487668 (2002-11-01), Thomas et al.
patent: 6567876 (2003-05-01), Stufflebeam
patent: 6785829 (2004-08-01), George et al.
patent: 6845462 (2005-01-01), Yatsuda et al.
patent: 7007187 (2006-02-01), Wilcox et al.
patent: 2002/0073351 (2002-06-01), Oh
patent: 2002/0104029 (2002-08-01), Fang
patent: 2002/0116650 (2002-08-01), Halepete et al.
patent: 2003/0058132 (2003-03-01), Yatsuda et al.
patent: 402280210 (1990-11-01), None
International Search Report from PCT/US2004/003352, mailed on Oct. 11, 2004.
Perveen Rehana
Rahman Fahmida
Trop Pruner & Hu P.C.
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