Reducing coupling effect on reference voltages when output...

Electronic digital logic circuitry – Interface – Supply voltage level shifting

Reexamination Certificate

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C326S068000, C326S080000

Reexamination Certificate

active

10710874

ABSTRACT:
Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the output signals. An inverted signal of the output signal is connected to the node through an impedance (e.g., capacitor) that stores energy. The inverted signal pulls the node in the opposite voltage level direction compared to the coupling effect of the output signal, thereby leaving the reference voltage substantially unchanged. By selecting the capacitance of the capacitor equaling the parasitic capacitance between the node and the output of the output buffer, coupling may be reduced substantially.

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patent: 6218854 (2001-04-01), Ko
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patent: 6556040 (2003-04-01), Whitworth
Hector Sanchez, Joshua Siegel, Carmine Nicoletta, James .P and Nissen ,Jose Alvarez, “A Versatile 3.3V/2.5V/1.8-V CMOS I/O Driver Built in a 0.2-um , 3.5nm Toz, 1.8-V CMOS Technology” In IEEE J. Solid State Circuits vol. 34,pp. 1501-1511,No. 11, Nov. 1999.
Changsik Yoo, Min-Kyu Kim, and Wonchan kim , “A Static Power Saving TTL-to-CMOS Input buffer” in IEEE Journal of Solid State Circuits. vol. 30, pp. 616-620, No. 5, May 1995.

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