Reducing core wake-up latency in a computer system

Details Reducing core wake-up latency in a computer system Reducing core wake-up latency in a computer system

2007-12-18

2009-10-13

Knoll, Clifford H (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Multimode interrupt processing

C713S330000

Reexamination Certificate

active

07603504

ABSTRACT:
A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect arrival of a first, second, and a third interrupt directed at a first, second, and a third core. The power control unit may check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete. The power control unit may then wake-up the second and the third core concurrently if the second interrupt occurs within the first period after the wake-up activity of the first core is complete. The first period may at least equal twice the time required for a first credit to be returned and next credit to be accepted.

REFERENCES:
patent: 5073943 (1991-12-01), Chapman
patent: 5758137 (1998-05-01), Armstrong et al.
patent: 6523073 (2003-02-01), Kammer et al.
patent: 2008/0010563 (2008-01-01), Nishimura
patent: 2008/0098246 (2008-04-01), Kim

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