Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-11
2003-07-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S637000, C438S638000
Reexamination Certificate
active
06586334
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of fabricating copper interconnects in semiconductor devices and more specifically to a reducing copper line resistivity.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects due to the significantly lowered resistivity of copper versus aluminum. The resistivity of copper is less than 1.8 &mgr;&OHgr;-cm for copper lines wider than 0.5 &mgr;m in linewidth. However, the value increases rapidly as the copper line/via dimension decreases. At 0.20 &mgr;m linewidth, the copper line resistivity was measured to be 2.15 &mgr;&OHgr;-cm. The increase in copper resistivity is expected to accelerate as the dimension continues to shrink. Simulations indicate that the copper resistivity will surpass aluminum resistivity of 2.8 &mgr;&OHgr;-cm at the 0.08 &mgr;m technology.
FIG. 1
displays the simulation results that show how quickly the resistivity rises as linewidth decreases using current copper interconnect approaches.
SUMMARY OF THE INVENTION
The invention reduces copper line resistivity by smoothing trench and via sidewalls. After the via and/or trench etches, the rough sidewalls are smoothed by depositing a thin layer of liner material. If desired, a directional etch may follow the deposition to remove liner material from the horizontal surfaces. Processing continues to form the copper interconnect with any desired barrier layers.
An advantage of the invention is providing a copper interconnect with reduced line resistivity for deep sub-quarter micron devices.
REFERENCES:
patent: 6217721 (2001-04-01), Xu et al.
patent: 6319822 (2001-11-01), Chen et al.
patent: 6326297 (2001-12-01), Vijayendran
patent: 6380628 (2002-04-01), Miller et al.
patent: 2001/0019884 (2001-09-01), Miller et al.
Brady III W. James
Garner Jacqueline J.
Gurley Lynne A.
Niebling John F.
Telecky , Jr. Frederick J.
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