Reducing contamination of semiconductor substrates during...

Details Reducing contamination of semiconductor substrates during... Reducing contamination of semiconductor substrates during...

2009-04-06

2011-10-18

Alanko, Anita (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S734000, C427S097600, C427S099200, C204S192250, C204S192350

Reexamination Certificate

active

08039400

ABSTRACT:
A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

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Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 030 847.1 dated Apr. 14, 2009.

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