Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-03-22
2002-02-26
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S697000, C438S700000, C438S723000
Reexamination Certificate
active
06350694
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing surface damage after the process of Chemical Mechanical Polishing (CMP) has been completed.
(2) Description of the Prior Art
Current semiconductor technology continues to improve device performance by reducing device feature dimensions and by providing denser packaging for the devices, reducing the length of inter-device interconnects. Parasitic influences are therewith reduced as are induced ohmic losses over interconnect lines.
Semiconductor device technology has progressed from Large Scale Integration (LSI) through Very Large Scale Integration (VLSI) to the present Ultra Large Scale Integration (ULSI). This technological evolution has affected not only devices and device features but has in addition greatly affected the manner and methods that are used to interconnect semiconductor devices and to package these devices once the devices are created.
Semiconductor devices that are created using VLSI technology contain a large variety of semiconductor and electrical components such as transistors of significantly different designs, resistors, capacitors and inductors that are formed on a chip that also contains digital processing capabilities, digital devices and analog devices with hybrid devices that process both digital and analog data. All of these devices however have in common that devices and device features must be interconnected before the device can be considered a complete, functional device. Processing dimensions of patterns that are created for the purpose of creating a semiconductor device have been decreasing year by year and are approaching submicron dimensions. Key to the creation of good interconnect metal is the planarity or surface flatness of the interconnect metal. This aspect of the creation of interconnect lines takes on even more urgency in applications where multiple layers of interconnect lines and line patterns are superimposed. Lack of planarity in a lower layer is in those cases further multiplied, this to the point where higher layers of interconnect become impossible to create (due to poor depth of focus for the photolithographic process that is required for the creation of these layers). To address this problem of surface planarity, a method of planarization, that is Chemical Mechanical Polishing or CMP, has been developed. A CMP technique is one of the techniques that has been developed to meet strict requirements for surface planarity as it applies to further device miniaturization. This technique is essential in performing planarization of insulating layers that are formed between overlying layers of conducting interconnect lines, for the formation of plugs, for the formation of buried metal interconnections and for the isolation of buried elements in semiconductor devices. The process of CMP is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate.
The use of chemical mechanical polishing to planarize semiconductor substrates has not met with universal acceptance, particularly where the process is used to remove high elevation features created during the fabrication of microelectronic circuitry on the substrate. One primary problem, which has limited the used of chemical mechanical polishing in the semiconductor industry, is the limited ability to predict, much less control, the rate and uniformity at which the process will remove material from the substrate. As a result, CMP is a labor intensive process, because the thickness and uniformity of the substrate must be constantly monitored to prevent over-polishing or inconsistent polishing of the surface of a substrate.
Current polishing practice uses a slurry that is inserted between the polishing medium, such as a polishing pad and the surface that is being polished. The slurry is primarily used to enhance the rate at which selected materials are removed from the substrate surface. It is basic that the slurry must be present in equal amount and having equally abrasive polishing characteristics across the surface that is being polished. This because it is highly desirable that the polishing of a semiconductor surface proceeds in a uniform and even manner across the surface that is being polished. To add further complexity to this requirement it must be realized that the polishing medium and the surface that is being polished are typically urged towards each other in order to enhance the abrasive polishing action. This urging together of the two surfaces makes an even distribution of the slurry that must be present between these surfaces even more difficult. One factor, which contributes to the unpredictability and non-uniformity of the polishing rate of the CMP process, is the non-homogeneous replenishment and therefore the non-homogeneous polishing action of slurry at the surface of the substrate and the polishing pad. The slurry, which is in contact with the substrate, reacts with selected materials on the surface of the substrate. As a result of this reaction the slurry becomes less abrasive and the polishing enhancing characteristics of the slurry are significantly altered. One approach to overcoming this problem is to continuously provide fresh slurry onto the polishing pad. Fresh slurry must, in order to achieve uniform polishing action across a surface, be present across this surface in equal amounts on all points of the polished surface.
In a typical CMP apparatus a polishing pad is attached to a circular polishing table, which rotates at a rate in the order of 1 to 100 m RPM. A wafer carrier is used to hold a wafer face down against the polishing pad. The wafer is held in place by applying a vacuum to the backside of the wafer. The wafer carrier also rotates, usually in the same direction as the polishing table, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table, the wafer traverses a circular polishing path over the polishing pad. A force is also applied in the downward vertical direction against the wafer, which presses the wafer against the polishing pad as it is being polished. The force is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft that is attached to the back of wafer carrier. Slurry is provided to the top of the polishing pad to further enhance the polishing action of polishing pad. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
When applying the CMP process to Intra Level Dielectric (ILD) and Inter Metal Dielectric (IMD) that are used for the manufacturing of semiconductor wafers, surface imperfections (micro-scratch) typically present a problem. Imperfections caused by micro-scratches in the ILD and IMD can range from 100 to 1000 EA for 200 mm. wafers, where an imperfection typically has a depth from 500 to 900 Å and a width of from 1000 to 3000 Å.
It is clear that the impact that the presence of micro-scratch has on the surface of an interconnect medium is dependent on the size of the interconnect medium. For the larger size devices within the semiconductor wafer, with dimensions of the interconnect lines of 0.35 &mgr;m or larger, the impact of micro-scratch may be relatively mild. For device sizes in the semiconductor wafer of 0.25 &mgr;m or less, micro-scratch may result in relative large imperfections in the surface of the wafer, large with respect to the size of the semiconductor devices. These imperfections will cause shorts between the metal lines in the devices while the imper
Bao Tien-I
Chang Weng
Jang Syun-Ming
Ackerman Stephen B.
Lebentritt Michael S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Reducing CMP scratch, dishing and erosion by post CMP etch... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reducing CMP scratch, dishing and erosion by post CMP etch..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing CMP scratch, dishing and erosion by post CMP etch... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2946516