Reduced wafer warpage in semiconductors by stress...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S618000, C438S624000, C438S638000, C257SE21579, C257SE21585

Reexamination Certificate

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08053354

ABSTRACT:
In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools.

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Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 054 069.2 dated Sep. 2, 2009.

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