Reduced verification complexity and power saving features in...

Details Reduced verification complexity and power saving features in... Reduced verification complexity and power saving features in...

2005-10-11

2005-10-11

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S340000, C712S208000, C712S214000

Reexamination Certificate

active

06954865

ABSTRACT:
An integrated circuit that uses a functional unit that outputs one set of values when in a power saving mode is provided. The functional unit, generally pipelined, is capable of being in the power saving mode dependent on an instruction decode/issue unit, and when in the power saving mode, the functional unit, using power saving mode circuitry, outputs one set of values as seen by components external to the functional unit regardless of the state the functional unit is in when the functional unit is initially put in the power saving mode.

REFERENCES:
patent: 4785393 (1988-11-01), Chu et al.
patent: 5944841 (1999-08-01), Christie
patent: 6000035 (1999-12-01), Matsushima et al.
patent: 6219796 (2001-04-01), Bartley
patent: 6647488 (2003-11-01), Takeno et al.
patent: 2002/0002664 (2002-01-01), Kuemerle
International Search Report for PCT/US 03/18876 (3 pages); and Notification of Transmittal of International Search Report (mailing date Jun. 24, 2004 ) (1 page).

Affiliated with

Also associated with

Rating

Reduced verification complexity and power saving features in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced verification complexity and power saving features in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced verification complexity and power saving features in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3490671