Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-03-23
2002-08-27
Lee, Thomas (Department: 2185)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C327S337000, C327S365000, C327S423000, C327S434000
Reexamination Certificate
active
06442633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of circuits.
Portions of the disclosure of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever. Sun, Sun Microsystems, the Sun logo, Solaris, Java, JavaOS, JavaStation, HotJava Views and all Java-based trademarks and logos are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.
2. Background Art
Computer systems are comprised of components that consist of millions of integrated circuits. Computer system performance can sometimes be greatly improved by improving the performance of individual circuits. One type of circuit in a computer system is referred to as a two-way data port. Current data port circuits are complex and have a relatively large number of transistors. It is desired to reduce the number of devices in a data port to improve the performance of data port circuits.
Data Port Operation
A data port is a circuit that has two inputs (A and B) and produces two outputs (D and E). The data port can be configured to have the data on the A input passed to the D output, with the data on the B input passed to the E output, or the data port can be configured to have the data on the A input passed to the E output, with the data on the B input passed to the D output. The operation of the data port is controlled by an input control signal C that determines the input/output configuration of the data port.
The logical configuration of a two way data port is illustrated in FIG.
1
. Referring to
FIG. 1
, a two way data port
100
is shown with A and B inputs
101
and
102
respectively. The D and E are shown as outputs
104
and
105
respectively. The control signal C is shown as signal
103
. In the embodiment shown, when signal C is asserted, the A and B inputs are routed to outputs D and E respectively. When the inverse of signal C is asserted, the A and B inputs are routed to outputs E and D respectively.
Prior Art Circuit Implementations
First Prior Art Embodiment—
FIG. 2
is an example of a first prior art implementation of the two way data port of FIG.
1
. Input signal A is coupled through inverter
202
to the input of standard cell circuit
203
.
1
and to the input of standard cell circuit
203
.
4
. Input B is coupled through inverter
206
to the input of standard cell
203
.
2
and to the input of standard cell
203
.
3
.
The outputs of standard cells
203
.
1
and
203
.
2
are coupled to D output
204
. The outputs of standard cells
203
.
3
and
203
.
4
are coupled to E output
205
. Standard cells
203
.
1
and
203
.
3
are enabled by signal CI
210
, and standard cells
203
.
2
and
203
.
4
are controlled by signal CB
211
. These signals are created when C input
207
is provided through inverter
208
to yield signal CB
211
and again through inverter
209
to yield signal CI
210
. When C input
207
is high, signal CI
210
is high and signal CB
211
is low. This enables standard cells
203
.
1
and
203
.
3
while disabling
203
.
2
and
203
.
4
. As a result, input A is coupled to output D and input B is coupled to output E.
When C input
207
is low, signal CI
210
is low and signal CB
211
is high. This enables standard cells
203
.
2
and
203
.
4
, disabling
203
.
1
and
203
.
3
. As a result, input A is now coupled to output E and input B is coupled to output D.
Each standard cell
203
.
1
through
203
.
4
of
FIG. 2
is implemented with the circuit of FIG.
3
.
FIG. 3
comprises PMOS transistors M
1
-M
7
and NMOS transistors M
8
-M
14
. The sources of PMOS transistors M
1
, M
2
and M
4
-M
7
are coupled to the upper voltage reference node. The sources of NMOS transistors M
8
, and M
10
-M
14
are coupled to the lower voltage reference node. Input E is applied to the gates of PMOS transistors M
1
and M
5
and NMOS transistors M
9
and M
11
. Input A is applied to the gates of PMOS transistor M
4
and NMOS transistor M
14
. Output node A′ (Y) is formed by the coupled drains of PMOS transistor M
7
and NMOS transistor M
8
. The drains of PMOS transistor M
1
and NMOS transistor M
11
are coupled to the gates of PMOS transistor M
2
and NMOS transistor M
12
to form node
4
. The drains of PMOS transistor M
4
and NMOS transistor M
14
are coupled to the gates of PMOS transistors M
3
, M
6
, M
13
and NMOS transistor M
10
to form node
5
. The drain of PMOS transistor M
2
is coupled to the source of PMOS transistor M
3
to form node
13
, and the drains of PMOS transistor M
3
and NMOS transistor M
12
are coupled to the gate of NMOS transistor M
8
and the drain of NMOS transistor M
13
to form node
2
. The drains of PMOS transistors M
5
and M
6
and NMOS transistor M
9
are coupled to the gate of PMOS transistor M
7
to form node
6
. The source of NMOS transistor M
9
is coupled to the drain of NMOS transistor M
10
to form node
12
.
A disadvantage of the circuit of
FIG. 3
is that each standard cell uses
14
transistors. With four cells in the data port,
56
transistors are required for each data port. The cell is a tristate circuit and is inherently a poor driver. It uses larger area, more stages of delays, higher input capacitance, and is vulnerable to CB/CI skew induced transient current contentions.
Second Prior Art Embodiment—
FIG. 4
illustrates a second prior art two way data port embodiment. The A input is coupled through inverter
402
to produce signal
405
coupled to the first input of standard cell
403
.
1
and to the second input of standard cell
403
.
2
. The B input is coupled through inverter
404
to produce signal
406
coupled to the first input of cell
403
.
2
and to the second input of cell
403
.
1
. Signal CI selects the first input of cells
403
.
1
and
403
.
2
, while signal CB selects the second input of cells
403
.
1
and
403
.
2
. The output of cell
403
.
1
is D output
407
and the output of cell
403
.
2
is E output
408
.
When signal CI is enabled, the first input of cells
403
.
1
and
403
.
2
is selected so that the A input is coupled to the D output
407
and the B input is coupled to the E output
408
. When signal CB is enabled, the second input of cells
403
.
1
and
403
.
2
is enabled so that the A input is coupled to the E output
408
and the B input is coupled to the D output
407
.
Each of cells
403
.
1
and
403
.
2
is comprised of the circuit of FIG.
5
.
FIG. 5
comprises PMOS transistors M
1
-M
4
and NMOS transistors M
5
-M
8
. The sources of PMOS transistors M
1
and M
2
are coupled to the upper voltage reference node. The drains of PMOS transistors M
1
and M
2
are coupled to the sources of PMOS transistors M
3
and M
4
to form node
7
. The drains of PMOS transistors M
3
and M
4
are coupled to the drains of NMOS transistors M
6
and M
7
to form output node Y. The sources of NMOS transistors M
6
and M
7
are coupled to the drains of transistors M
5
and M
8
, respectively, and the sources of transistors M
5
and M
8
are coupled to the lower voltage reference node. Input A is applied to the gates of transistors M
3
and M
7
, input B is applied to the gates of transistors M
4
and M
8
, input C is applied to the gate of transistors M
2
and M
6
, and input D is applied to the gates of transistors of M
1
and M
5
.
A disadvantage of the circuit of
FIG. 5
is the number of transistors. With two cells required, a total of
16
transistors is required for the data port. Also, the circuit is a poor driver. It involves two NTx or PTx for tf or tr switching. It also has double input gate load to the previous stage.
SUMMARY OF THE INVENTION
The present invention provides a best circuit configuration for data port solutions. One embodiment uses a pair of transmission gates as bridges to realize 2×2×D (M×N×D) logic switchi
Du Thuan
Gunnison McKay & Hodgson, L.L.P.
Lee Thomas
McKay Philip J.
Sun Microsystems Inc.
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