Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-02-01
2004-10-12
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S055000, C326S093000, C326S113000
Reexamination Certificate
active
06803793
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a low power CMOS circuit, and particularly a low-power SOI device.
2. Description of the Related Art
Power reduction is important in modern VLSI design due to the increasing operating frequencies and circuit densities, and the emergence of new mobile applications such as portable terminals and consumer products. CMOS is one of the most low power logic styles because the circuits consume power only when the logic states change and it is widely used in the modern LSI. However, as the technology is scaling and the number of the transistors is increasing, the dynamic power consumption is increasing rapidly. Decreasing the supply voltage is the easiest way to reduce power consumption in CMOS circuits because switching power is proportional to the square of the supply voltage.
However, reducing the supply voltage degrades circuit speed due to the super-linear reduction of transistor current. The voltage applied to transistor gate determines transistor conductance and larger conductance can charge up the output node faster. So if the supply voltage is reduced, the voltage applied to the gate is also reduced and thus significantly degrade the circuit speed. To recover this slow down, the reduction of threshold voltage of the transistor is effective.
However, the reduction of the threshold voltage leads to increasing sub-threshold leakage current and the leakage current increases the stand-by power consumption of LSI, which is not acceptable for the application of consumer products such as a portable terminal powered from a battery. Recently, since the threshold voltage of the transistor may be selected so as to be rather low, a further reduction of the threshold voltage may be difficult.
Another technique for lowering power consumption without reducing the supply voltage is to lower a swing voltage. In conventional low swing voltage circuits, dynamic low swing drivers are used and during the evaluation of the logic, at least one of the net or signal becomes floating. In the design of the data path, this net usually becomes long and a lot of other nets go over the net. A coupling noise to these nets easily causes failure of slow down of the circuits.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a new low power CMOS circuit, in which the supply voltage and/or the threshold voltage is not reduced, and power reduction can be achieved without the cost of degrading the circuit speed.
It is another and more specific object of the present invention to provide an SOI device utilizing the low-power CMOS circuit.
In order to achieve the above objects according to the present invention, a circuit is proposed, in which the supply voltage is not reduced, but only swing voltage is reduced. As the power consumption is proportional to the swing voltage, dynamic power reduction is expected by reducing the swing voltage. Since the supply voltage is not reduced, the voltage applied to the gate is not reduced and the circuit speed is maintained. The charge recycling scheme is also applied to the circuits. In typical CMOS circuits, all the charge stored at the output node is dumped to ground when the logic state changes. A charge recycling circuit can re-use the charge stored in the previous cycle and can reduce the power consumption by half.
The circuit according to the present invention has a configuration using both reduced swing voltage and charge recycling techniques. This scheme is called Low Swing Charge Recycling (LSCR) style.
In order to achieve the above object, a circuit arrangement is disclosed, which includes:
a complementary pass transistor logic;
a static driver connected to the complementary pass transistor logic and driving complementary input nodes to each other of the complementary pass transistor logic by a low swing voltage; and
a charge recycling circuit connected to the complementary pass transistor logic and performing charge sharing between the complementary input nodes when the complementary pass transistor logic is not driven by the static driver.
According to the present invention, since the static driver can reduce the swing voltage while maintaining the supply voltage and the charge recycling circuit can reduce the charge provided from the supply by half, the circuit can lower the power consumption without being suffered from circuit speed degradation. Furthermore, since the driver of the present invention is static, all nets or signals stay static during evaluation of the logic. In other word, all the nets have a path to the supply or the ground during evaluation and they are robust against coupling from other nets.
With the above-described circuit arrangement, a swing level of the low swing voltage ranges from a ground voltage level to a supply voltage level minus a threshold voltage level.
Moreover, with the above-described circuit arrangement, the static driver is formed of a plurality of transistors connected in series
In order to achieve the object, a low swing charge recycling circuit arrangement is disclosed, which includes:
a complementary pass gate stage having driving inputs to receive each of driving input signals, having complementary outputs to produce an output signal on one hand and a complementary-output signal on the other and determining a logic operation of the circuit arrangement;
a static low swing driver stage having a signal input to receive an input signal, having a clock input to receive a clock signal, and having complementary outputs to produce low swing complementary signals to each output to be provided to the driving inputs of the complementary pass gate when the clock signal is in one of two states; and
an equalization stage being connected to the complementary outputs, having a clock input to receive the clock signal and producing complementary signals to the driving inputs of the complementary pass gate stage when the clock signal is in the other state, whereby a charge shared signal of an intermediate voltage level between those of the complementary outputs is shared between the driving inputs.
With the above-described circuit arrangement, the static low swing driver stage is operated to reduce a swing voltage applied to a source of the complementary pass gate stage without changing the supply, voltage, so that the power consumption can be saved. Since the level of the driving input signals to the pass gate stage for logic operation does not have to be lowered, the circuit speed can be maintained without degrading a driving performance for the transistor. When the static low swing driver stage is not operated the complementary outputs of the drive are closed, the equalization stage is alternatively operated and allows the charge sharing between the driving inputs of the pass gate stage, and thus resulting in the power consumption reduction. The equalization stage performs the charge sharing between the complementary driving inputs by connecting the driving inputs and pre-charges both driving inputs to a certain intermediate voltage between a driving voltage level and a ground level. This allows an effective logic signal swing to be approximately a half of that of the circuit without charge recycling and results in low power consumption.
With the above-described circuit arrangement, the driver stage is designed to be static. As a result, the drive stage is operated such that all the nodes are driven by the supply potential or ground potential during the evaluation, and thus the driver stage has no floating nodes. Therefore, the circuit arrangement will not be likely to cause malfunction nor signal delay.
It may be particularly advantageous that the above-mentioned low swing charge recycling circuit arrangement is applied to an SOI device. The SOI transistor is fabricated on insulator and has less parasitic capacitance. This is a good feature for achieving low power, because the excessive parasitic capacitance do not need to charge/discharge. The body of these devices is isolated from each other and cann
Chang Daniel D.
Christie Parker & Hale LLP
Fujitsu Limited
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