Reduced surface field technique for semiconductor devices

Details Reduced surface field technique for semiconductor devices Reduced surface field technique for semiconductor devices

2005-12-27

2005-12-27

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

In integrated circuit

C257S493000

Reexamination Certificate

active

06979875

ABSTRACT:
A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.

REFERENCES:
patent: 5306652 (1994-04-01), Kwon et al.
patent: 5382535 (1995-01-01), Malhi et al.
patent: 5498554 (1996-03-01), Mei
patent: 5501994 (1996-03-01), Mei
patent: 5512495 (1996-04-01), Mei et al.
patent: 5585660 (1996-12-01), Mei
patent: 5739061 (1998-04-01), Kitamura et al.
patent: 5801420 (1998-09-01), Fujishima
patent: 5852314 (1998-12-01), Depetro et al.
patent: 6211552 (2001-04-01), Efland et al.
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 6693339 (2004-02-01), Khemka et al.
patent: 6888210 (2005-05-01), Jeon et al.
Kwon, T.H., et al., “Newly designed isolated RESURF LDMOS transistor BCD process provides 20 V vertical NPN transistor”, Jun. 24-6, 2002, 2002 60th DRC, pp. 67-68.
Kim, M.H., et al., “A 650V rated RESURF-type LDMOS Employing an Internal Clamping Diode for Induced Bulk Breakdown withot EPI Layer”, Jun. 4-7, 2001, Power Semiconductor Devices and ICs, 13th Internal Symposium, pp. 347-350.
“Silicon Carbide Lateral Power MOSFETs,” Jan Spitz, M.R. Melloch and J.A. Cooper, Jr., from website address http://www.ecn.purdue.edu/WBG/Device—Research/LDMOSFETs/Index.html, 3 pages.
“Design of a Lateral MOSFET in Silicon Carbide,” Chris Sanders, Janna Bonds, Elmer Durrell, and Wendy Evans, Design document submitted to Professor Joseph Picone, Department of Electrical and Computer Engineering, Mississippi State University, Mar. 21, 2000, pp. 1-43.
“Linearly Graded Doping Drift Region: A Novel Lateral Voltage-sustaining Layer Used for Improvement of RESURF LDMOS Transistor Performances,” Jin He1,2, Xuemei Xi2, Mansun Chan2, Chenming Hu2, Yingxue Li1, Zhang Xing1and Ru Huang1,Semiconductor Science and Technology, vol. 17, 2002, pp.
“The Insulated Gate Bipolar Transistor (IGBT),” from website address http://www.elec.gla.ac.uk/groups/dev—mod/papers/igbt/igbt.html, 3 pages.

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