Reduced size plate layer improves misalignments for CUB DRAM

Details Reduced size plate layer improves misalignments for CUB DRAM Reduced size plate layer improves misalignments for CUB DRAM

2005-03-29

2005-03-29

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000

Reexamination Certificate

active

06873001

ABSTRACT:
In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.

REFERENCES:
patent: 6020235 (2000-02-01), Chang

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