Reduced size integrated circuits and methods using test pads loc

Details Reduced size integrated circuits and methods using test pads loc Reduced size integrated circuits and methods using test pads loc

1998-11-30

2000-09-19

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257786, 257 48, H01L 2348

Patent

active

061216771

ABSTRACT:
Integrated circuit regions are formed on an integrated circuit wafer. The integrated circuit wafer includes scribe regions located between the integrated circuit regions, the scribe regions include test pads that are electrically connected to the test circuits of integrated circuit regions via conductive lines. Test functions are provided to the test circuits in the integrated circuit regions via the test pads to determine the operability of the integrated circuit regions. The integrated circuit regions are separated from the plurality of scribe regions and the plurality of test pads located therein. Separating the integrated circuit regions from the scribe regions and the test pads, thereby may allow a reduction in the number of pads in the integrated circuits and a corresponding decrease in the size of respective integrated circuit packages.

REFERENCES:
patent: 5053700 (1991-10-01), Parrish
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5285082 (1994-02-01), Axer
patent: 5391892 (1995-02-01), Devereaux et al.
patent: 5477062 (1995-12-01), Natsume
patent: 5483175 (1996-01-01), Ahmad et al.
patent: 5506499 (1996-04-01), Puar
patent: 5896040 (1999-04-01), Brannigan et al.
patent: 5923047 (1999-07-01), Chia et al.

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