Reduced size etching method for integrated circuits

Details Reduced size etching method for integrated circuits Reduced size etching method for integrated circuits

1995-06-14

1999-06-15

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438713, 438736, 438717, H01L 21302

Patent

active

059131489

ABSTRACT:
A method of semiconductor fabrication which permits the creation of openings which have dimensions smaller than what may be achieved by conventional lithography. In an illustrative processing sequence, a pattern transfer material is deposited upon another material layer. The pattern transfer material is covered with photoresist which is subsequently patterned. With the patterned photoresist as a mask, the pattern transfer material is etched with a process which creates inward sloping walls. Then the pattern transfer material is used as a mask to etch the underlying material. The inward sloping walls of the pattern transfer material permit creation of an opening in the underlying material which is smaller than the corresponding opening in the photoresist. The method may also be used to create trenches or field oxides which have dimensions smaller than those achievable by lithography.

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Hitchner, J., Polyimide Layers Having Tapered via Holes, IBM Tech. Discl. Bull., vol. 20, No. 4, Sep. 1977, p. 1384.

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