Reduced silicon gouging and common source line resistance in...

Details Reduced silicon gouging and common source line resistance in... Reduced silicon gouging and common source line resistance in...

2005-10-11

2005-10-11

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S723000

Reexamination Certificate

active

06953752

ABSTRACT:
In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.

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patent: 6383921 (2002-05-01), Chan et al.
patent: 6479859 (2002-11-01), Hsieh et al.
patent: 6570214 (2003-05-01), Wu

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